Intel to make ambitious claims for Prescott Pentium 4
WHEN INTEL INTROS Pentium 4 Prescotts and a 3.40MHz Extreme Edition chip in early February, it will herald better hyperthreading, SSE software support and architectural changes to convince the world+dog to shift.
That's emerged from briefings it's given selected journalists prepared to keep their mouths shut here in Las Vegas over the last two days.
As we've already reported, the P4Es, which have 1MB of on die cache and are prepared on a shrunk 90 nanometer process, will come at speeds of 3.40GHz, 3.20GHz, 3GHz and 2.80GHz, displacing the current range of chips.
There's better hyperthreading, 12K micro operation instruction cache and those famous 13 new instructions. And the chips use strained silicon and low K CDO.
The 90 nano process includes seven layers of copper interconnect compared to six layers in the .13µ core, uses nickel rather than cobalt silicide, has 1.15u2 SRAM cells, and includes 193 nano lithography.
The 13 Louis Burns special opcodes look after thread synchronization, SIMD FP, video encoding, complex arithmetic and FP to integer conversion.
