Intel to demo fanless, cool 5GHz chip
Source: The Inquirer
CHIP GIANT INTEL confirmed the large caches it will include on future versions of the Itanium and has also further explained its tie in with Ovonics on these chips, first revealed here some months ago.
Intel is delivering eleven papers at the Solid State conference. Along with this, Intel has now formally released details of the 3MB cache on chip which it claims will deliver 1.5 to two times performance over the current designs.
The low latency level three cache which will be included in the McKinley design is expected to give better performance for the processor, which will be used in servers.
