IBM's new transactional memory: make-or-break time for multithreaded revolution

The BlueGene/Q processors that will power the 20 petaflops Sequoia supercomputer being built by IBM for Lawrence Livermore National Labs will be the first commercial processors to include hardware support for transactional memory. Transactional memory could prove to be a versatile solution to many of the issues that currently make highly scalable parallel programming a difficult task. Most research so far has been done on software-based transactional memory implementations. The BlueGene/Q-powered supercomputer will allow a much more extensive real-world testing of the technology and concepts. The inclusion of the feature was revealed at Hot Chips last week.

BlueGene/Q itself is a multicore 64-bit PowerPC-based system-on-chip based on IBM's multicore-oriented, 4-way multithreaded PowerPC A2 design. Each 1.47 billion transistor chip includes 18 cores. Sixteen will be used for running actual computations, one will be used for running the operating system, and the final core will be used to improve chip reliability. For BlueGene/Q, a quad floating point unit, capable of up to four double-precision floating point operations at a time, has been added to every A2 core. At the intended 1.6GHz clock speed, each chip will be capable of a total of 204.8 GFLOPS within a 55 W power envelope. The chips also include memory controllers and I/O connectivity.