Bandwidth in the news
Got this from Arstechnica:
"There's nothing like a good, old-fashioned standards war to get competition (or confusion) brewin' again, and that seems to be what Intel is proposing. They've thrown down the gauntlet to AMD's HyperTransport, with a rival, as yet undefined specification intended to replace PCI in desktop computers. From the EET coverage (see also the CNET coverage here):
At the recent Intel Developer Forum (IDF), Louis Burns, general manager of Intel's Desktop Platforms Group, detonated a silent bomb when he announced that Intel was working on its third-generation I/O spec, a replacement for PCI. The spec, which looks to prepare I/O technology for the coming age of 10-GHz processors, will move away from shared buses, as in the Infiniband initiative for servers.
"Third-generation I/O architecture has to be full serial; it has to be a point-to-point connection to support the hyperspeeds we're going to be driving this at," Burns said at the time. "We want to have the absolute smallest number of pins with the absolute maximum bandwidth." Also, he said, the bus "has to be scalable to greater than 10 GHz, and it has to be flexible to really adopt the needs of the end user, the OEM and the industry at large."
Notice the bit about the smallest number of pins at the maximum bandwidth. What does that remind you of? If you said Rambus, then you were right on. I wonder how closely Rambus will be involved in the drafting of this spec--will they use any Rambus IP? The spec is purported to be open, and I don't imagine that they'll want to charge royalties for its use (since they're competing directly with the royalty-free HyperTransport); so for those reasons you'd think that they'd stay away from Rambus' IP. But the way this is being described sounds right up Rambus' alley. Anyway, time will tell.
And speaking of AMD's HyperTransport, their affiliate, API NetWorks, just released a bridge chip that lets a HyperTransport-based system use a legacy PCI bus. This fits in with AMD's stated goal of maintaining backwards compatibility with existing PCI devices and software, a goal that Intel doesn't share for its new spec."
